A discussion about all things related to FPGA design and verification
Welcome to the GateRocket news page. As we strive to deliver new and innovative technology for FPGA verification, we will periodically share our progress along the way in the form of news or general postings.
Check in here to see a news summary of GateRocket news and events.
Bedford, Mass. – Jan. 8, 2008: GateRocket’s RocketDrive™ made the 2007 top products lists in both EDN and Electronic Design magazines. EDN announced its Top 100 products in the Dec. 14 issue, and Electronic Design highlighted RocketDrive in its “Best Electronic Design” year end special on Dec. 3. The innovative RocketDrive was launched in April 2007.
“It’s a thrill to be recognized along with some of the industry’s great innovators by the leading electronics journals,” said Dave Orecchio, GateRocket president and CEO. “Many thanks to the editors for this great honor.”
In 2008 there will be nearly 95,000 new FPGA design projects according to Gartner/Dataquest, 32 times that of ASICs. While verification and debug of an FPGA is as challenging as any modern ASIC design, until RocketDrive there was no practical and economical solution to this daunting verification and debug problem.
The RocketDrive Device Native™ verification and debug solution is powered by the speed of hardware with the accuracy of the true chip behavior. An industry first, RocketDrive offers the ability to exhaustively validate and test an FPGA design before committing to production, enabling shorter product development times, higher product quality and improved ability to meet or exceed the requirements of today’s demanding marketplace.
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GateRocket’s solution allows the verification engineer to place any portions or all of the FPGA design into the RocketDrive and automatically integrate it into their existing simulation environment. This allows the FPGA to be used natively to (1) speed verification by replacing FPGA models with actual hardware; (2) investigate hardware bugs and test alternatives; and (3) run application level software against a Device Native representation of the design.
To learn more, please visit GateRocket’s web site and request a white paper or a demonstration.
GATEROCKET BRINGING FPGA VERIFICATION BREAKTHROUGH TO DAC
Bedford, Mass. – May 10, 2007: Startup GateRocket is bringing its breakthrough FPGA verification product – RocketDrive – to the electronic design community’s premier event, the Design Automation Conference (DAC). The DAC event is held from June 4th through the 8th at the San Diego, California Convention Center. GateRocket will exhibit in booth 2559. To request a Demonstration, please register at the GateRocket web site.
In 2007 there will be nearly 89,000 FPGA design starts according to Gartner/Dataquest, some 25 times that of ASICs. While verifying an FPGA is as challenging as any modern ASIC design, until RocketDrive there was no practical and economical solution to this daunting problem.
The RocketDrive Device Native verification solution is powered by the speed of hardware, the accuracy of the true chip behavior and the unbounded scalability of a system prototype. An EDA first, RocketDrive offers the ability to exhaustively validate and test an FPGA design before committing to production, enabling shorter product development times, higher product quality and improved performance to meet or exceed the requirements of today’s demanding marketplace. GateRocket’s software allows the verification engineer to place any portions of the FPGA design into the RocketDrive and integrate it to their existing simulation platform. This allows the FPGA to be used natively to (1) speed verification by replacing FPGA models with actual hardware; (2) investigate hardware bugs and test alternatives; and (3) run application level software against a Device Native representation of the design.
The GateRocket team looks forward to seeing you at the conference.
GATEROCKET DELIVERS THE EDA INDUSTRY’S FIRST DEVICE NATIVE VERIFICATION SOLUTION FOR ADVANCED FPGAs
- Ups Speed, Accuracy, Scalability in FPGA Design -
Bedford, Mass. – April 23, 2007: GateRocket™ Inc. today announced availability of the industry’s first Device Native™ verification product that gives Field Programmable Gate Array (FPGA) designers the power to validate designs with one to two orders of magnitude faster simulation, and realize actual device behavior early in the design process. RocketDrive™ is a hardware and software solution that adds significant value to existing design verification environments without a change in design flow or verification methodology.
RocketDrive: The RocketDrive Device Native verification solution is powered by the speed of hardware, the accuracy of the true chip behavior and the unbounded scalability of a system prototype. An EDA first, RocketDrive offers the ability to exhaustively validate and test an FPGA design before committing to production, enabling shorter product development times, higher product quality and improved performance to meet or exceed the requirements of today’s demanding marketplace. GateRocket’s software allows the verification engineer to place any portions of the FPGA design into the RocketDrive and link it to his or her existing simulation platform. This allows the FPGA to be used natively to (1) speed verification by replacing FPGA models with actual hardware; (2) investigate hardware bugs and test alternatives; and (3) run application level software against a Device Native representation of the design.
Traditional emulation environments strive to be technology independent, but suffer from long and arduous startup efforts for each project and produce inaccurate results. GateRocket’s new approach leverages the strength and uniqueness of the FPGA device and the flexibility of popular simulators to deliver a unique and accurate verification solution for these advanced design projects.
In addition, the RocketDrive enables rapid, accurate analysis of IP components by removing the need for special and inaccurate software models since the IP resides directly in the target FPGA device that is in the RocketDrive. For the first time, the designer sees the real on-chip IP behavior while operating within their existing flexible simulation and test verification environment.
“When making the transition from ASIC to FPGA design, I soon realized there was a serious lack of tools to verify and test these sophisticated devices,” said Chris Schalick, GateRocket founder, Vice President of Engineering and CTO. “I had an idea and the passion to address this acute debugging and verification problem, so that’s when I started GateRocket to solve this industry dilemma and serve this fast-growing market.”
Integrated Solution: The RocketDrive takes minutes to install in any Linux PC and integrates seamlessly with the user’s existing design and verification environment. The RocketDrive complements design tools from all leading EDA vendors including Cadence Design Systems (CDN), Mentor Graphics Corp. (MENT), Synopsys, Inc. (SNPS), Synplicity, Inc. (SYNP), and the FPGA vendor tools from Altera Corp. (ALTR) and Xilinx, Inc. (XLNX).
Changing Marketplace: As FPGA devices become more advanced they disruptively capture more and more of the ASIC marketplace. The FPGA market, dominated by Altera and Xilinx, has some 25 times the number of design starts than that of the ASIC market according to Gartner/Dataquest. The classical ASIC design and verification bottleneck still exists in FPGA design, yet till now no adequate tools have been available to address this burning market need. A significant commercial opportunity exists to address the design and verification bottleneck for these sophisticated FPGA devices.
“Electronics companies use FPGAs to miniaturize their products while significantly increasing features to meet market demand and create new markets; however electronic design engineers face a crisis in their inability to adequately verify and test these increasingly complex designs,” said Dave Orecchio, GateRocket’s President and CEO. “GateRocket’s solution addresses this problem with the unique and highly productive Device Native approach that can cut in half the time it takes to develop the electronic products we use every minute of every day,” he added.
Pricing and Availability: RocketDrives are immediately available for the Altera Stratix II and the Xilinx Virtex 4 family of devices. Contact GateRocket to learn more.
GateRocket at DAC: GateRocket will be exhibiting at the 2007 Design Automation Conference in San Diego California (June 4 - 7), Booth 2559. To register for a GateRocket Demo at DAC, please register on the GateRocket web site.
GATEROCKET SECURES SERIES A FINANCING ROUND LED BY COMMON ANGELS
- Appoints Dave Orecchio as President and CEO - Establishes Advisory Board -
Bedford, Massachusetts, September 15, 2006: GateRocket, Inc. today announced that it has secured $1,250,000 Series-A financing. The round was led by the prestigious CommonAngels with participation from a consortium of several other angel groups in the New England area including Beacon Angels, Cherrystone, Granite State Angels, Launchpad, Maine Angels and North Country Angels.
GateRocket Leadership: With the financing, GateRocket rounds out its executive management with the appointment of Dave Orecchio as President and CEO. Dave has 24 years of semiconductor industry experience at four venture backed companies with a focus on semiconductors, ASIC and FPGA design and development. His leadership brought three of the four companies to successful exits for the investors and stakeholders. Prior to GateRocket, Dave held executive positions in marketing, sales and general management at LTX, Viewlogic Systems, Inc, Synopsys, Innoveda, Parametric Technologies and DAFCA.
“When I reviewed the GateRocket product and vision, I saw an opportunity to create a great company built on the foundation of a truly groundbreaking product,” said Dave Orecchio, GateRocket’s President and CEO. “It is seldom where you find the perfect storm of the right technology at the right time with a fantastic team to execute on its vision. GateRocket has all of these properties,” he added.
Outside Directors: GateRocket has well established world-class leadership with outside board members and EDA and technology luminaries Alain Hanover and Jim Daniell.
Alain Hanover, was the founder and CEO of Incert Software Corporation and Viewlogic Systems, Inc., and is currently CEO at Navigator Technology Ventures.
Jim Daniell, a serial entrepreneur, was COO at AT&T’s Network Commerce Services, and held leadership roles at several startup companies before joining Echelon Ventures as Managing Director.
Advisory Board: GateRocket gains significant benefit from its technical advisory board, one with industry veterans with experience in EDA startups, business development, and finance. The Advisory Board includes Michael D’Amour, Brad Hafer, John McFee and Stacy Swider.
Mike D’Amour is COO at DRC Computer Corp. Mike is best known for his founding of Quickturn Design Systems, Inc., where he served as CEO, Chairman, and Executive VP of R&D. Mike led the company to a successful IPO and later an acquisition by Cadence Design Systems, Inc.
Brad Hafer is Managing Director at Minuteman Advisory Partners, LLC, a strategy consulting firm focused on high-tech corporate development. Brad was most recently VP of Corporate Development at Matrix One.
John MacFee is CFO at eDialog, Inc. In his many start-up experiences, John played a significant leadership role in their early stage development, rapid growth and subsequent initial public offerings.
Stacy Swider is an entrepreneur and consultant to high technology companies in the Boston area. Stacy provided business leadership for GateRocket from inception to the acquisition of financing and now plays an important role as advisor to GateRocket.
GATEROCKET PRESENTS INNOVATIVE CONCEPTS AT DVCON
- MERGING ASIC AND FPGA DESIGN TECHNIQUES TO CUT DESIGN TIME -
Bedford, Massachusetts, February, 2005: GateRocket, Inc. today announced participation in DVCon and the presentation of a paper titled MERGING ASIC AND FPGA DESIGN TECHNIQUES TO CUT DESIGN TIME. The paper will be presented by GateRocket Founder Chris Schalick on Tuesday February 15th in Session 6 - Advances in Design.
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