GateRocket Introduces RocketDrive - Device Native Verification for FPGAs
April 23rd, 2007 by Dave
GATEROCKET DELIVERS THE EDA INDUSTRY’S FIRST DEVICE NATIVE VERIFICATION SOLUTION FOR ADVANCED FPGAs
- Ups Speed, Accuracy, Scalability in FPGA Design -
Bedford, Mass. – April 23, 2007: GateRocket™ Inc. today announced availability of the industry’s first Device Native™ verification product that gives Field Programmable Gate Array (FPGA) designers the power to validate designs with one to two orders of magnitude faster simulation, and realize actual device behavior early in the design process. RocketDrive™ is a hardware and software solution that adds significant value to existing design verification environments without a change in design flow or verification methodology.
RocketDrive: The RocketDrive Device Native verification solution is powered by the speed of hardware, the accuracy of the true chip behavior and the unbounded scalability of a system prototype. An EDA first, RocketDrive offers the ability to exhaustively validate and test an FPGA design before committing to production, enabling shorter product development times, higher product quality and improved performance to meet or exceed the requirements of today’s demanding marketplace. GateRocket’s software allows the verification engineer to place any portions of the FPGA design into the RocketDrive and link it to his or her existing simulation platform. This allows the FPGA to be used natively to (1) speed verification by replacing FPGA models with actual hardware; (2) investigate hardware bugs and test alternatives; and (3) run application level software against a Device Native representation of the design.
Traditional emulation environments strive to be technology independent, but suffer from long and arduous startup efforts for each project and produce inaccurate results. GateRocket’s new approach leverages the strength and uniqueness of the FPGA device and the flexibility of popular simulators to deliver a unique and accurate verification solution for these advanced design projects.
In addition, the RocketDrive enables rapid, accurate analysis of IP components by removing the need for special and inaccurate software models since the IP resides directly in the target FPGA device that is in the RocketDrive. For the first time, the designer sees the real on-chip IP behavior while operating within their existing flexible simulation and test verification environment.
“When making the transition from ASIC to FPGA design, I soon realized there was a serious lack of tools to verify and test these sophisticated devices,” said Chris Schalick, GateRocket founder, Vice President of Engineering and CTO. “I had an idea and the passion to address this acute debugging and verification problem, so that’s when I started GateRocket to solve this industry dilemma and serve this fast-growing market.”
Integrated Solution: The RocketDrive takes minutes to install in any Linux PC and integrates seamlessly with the user’s existing design and verification environment. The RocketDrive complements design tools from all leading EDA vendors including Cadence Design Systems (CDN), Mentor Graphics Corp. (MENT), Synopsys, Inc. (SNPS), Synplicity, Inc. (SYNP), and the FPGA vendor tools from Altera Corp. (ALTR) and Xilinx, Inc. (XLNX).
Changing Marketplace: As FPGA devices become more advanced they disruptively capture more and more of the ASIC marketplace. The FPGA market, dominated by Altera and Xilinx, has some 25 times the number of design starts than that of the ASIC market according to Gartner/Dataquest. The classical ASIC design and verification bottleneck still exists in FPGA design, yet till now no adequate tools have been available to address this burning market need. A significant commercial opportunity exists to address the design and verification bottleneck for these sophisticated FPGA devices.
“Electronics companies use FPGAs to miniaturize their products while significantly increasing features to meet market demand and create new markets; however electronic design engineers face a crisis in their inability to adequately verify and test these increasingly complex designs,” said Dave Orecchio, GateRocket’s President and CEO. “GateRocket’s solution addresses this problem with the unique and highly productive Device Native approach that can cut in half the time it takes to develop the electronic products we use every minute of every day,” he added.
Pricing and Availability: RocketDrives are immediately available for the Altera Stratix II and the Xilinx Virtex 4 family of devices. Contact GateRocket to learn more.
GateRocket at DAC: GateRocket will be exhibiting at the 2007 Design Automation Conference in San Diego California (June 4 - 7), Booth 2559. To register for a GateRocket Demo at DAC, please register on the GateRocket web site.
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Michael D'Amour Says
In FPGA design,the high-speed interfaces are the toughest part. The pins have seemingly dozens of modes and other selection criteria. If, for example, you select a pin with the wrong clock capability, your board layout is toast. Hammer testing SSO is also important on DDR interfaces and the like.
It’s ingenious to use an FPGA to drive a like copy, ensuring that you can really test all the true drive strengths and speeds. Along with full at-speed emulation and simulator interfacing, really a very useful tool.
Apr 26th, 2007 at 8:26 pm
Dave Says
The electronics industry trade press has comprehensively covered the GateRocket RocketDrive product launch. For your convenience, here are links to the coverage we know about:
May 6th, 2007 at 1:50 pm